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www.fairchildsemi.com features 10-bit resolution 40 msps low power: 380 mw high signal-to-noise ratio: 58db internal track-and-hold built-in reference single +5volt power supply applications video digitizing ccd imaging scanners and cameras set-top boxes medical imaging cable modems test instrumentation description the TMC1185 is a high performance, low power, 10-bit 40 msps analog-to-digital converter. the monolithic converter includes a 10 bit quantizer with internal track-and-hold, ref- erence, and power down mode. inputs can be con?ured to accept either differential or single-ended inputs. it is fabri- cated in low power submicron cmos and operates from a single +5 volt power supply, dissipating only 380mw. the TMC1185 is designed with digital error correction, to provide excellent nyquist differential linearity performance for demanding imaging applications. low distortion, high snr and high oversampling capability gives the TMC1185 the margin needed for video and telecommunication applica- tions. this a/d convertor supports sampling rates up to 40 msps. it is available in a 28-pin soic package. TMC1185 10-bit, 40 msps sampling analog-to-digital converter block diagram pipeline a/d timing circuitry error correction logic 3-state outputs t/h 10-bit digital data clk +1.25v +3.25v msbi oe in in reft cm refb rev. 1.0.0
TMC1185 product specification 2 functional description the TMC1185 is a high speed sampling analog-to-digital converter with pipelining. it uses a fully differential architec- ture and digital error correction to guarantee 10-bit resolu- tion. the differential track/hold circuit is shown in figure 1. the switches are controlled by an internal clock which has a non-overlapping two phase signal, f 1 and f 2. at the sampling time, the input signal is sampled on the bottom plates of the input capacitors. in the next clock phase, f 2, the bottom plates of the input capacitors are connected together and the feedback capacitors are switched to the op amp output. at this time the charge redistributes from c i to c h , completing one track/hold cycle. the differential output is a held dc representation of the analog input at the sample time. the track/hold circuit can also convert a single-ended input signal into a fully differential signal for the quantizer. the pipelined quantizer architecture has 9 stages with each stage containing a two-bit quantizer and a two bit digital-to- analog converter, as shown in figure 2. each two-bit quantizer stage converts on the edge of the sub-clock, which is twice the frequency of the externally applied clock. the output of each quantizer is fed into its own delay line to figure 2. pipeline a/d architecture b9 (msb) b8 b7 b6 b5 b4 b3 b2 b1 b0 (lsb) 2-bit dac 2-bit flash input t/h digital delay x2 x2 65-1185-03 2-bit dac 2-bit flash digital delay 2-bit flash digital delay 2-bit dac 2-bit flash digital delay x2 digital error correction in in stage 1 stage 2 stage 8 stage 9 s + s s + figure 1. input track/hold configuration with timing signals f 1 f 1 f 2 f 1 f 1 f 1 f 1 f 1 f 2 f 1 f 2 f 1 f 2 in 65-1185-02 in out out op amp bias v cm op amp bias v cm c h c i c i c h input clock (50%) internal non-overlapping clock
product specification TMC1185 3 time-align it with the data created from the following quantizer stages. this aligned data is fed into a digital error correction circuit which can adjust the output data based on the information found on the redundant bits. this technique gives the TMC1185 excellent differential linearity and guarantees no missing codes at the 10-bit level. the output data is available in straight offset binary (sob) or binary twos complement (btc) format. the analog input and internal reference the analog input of the TMC1185 can be con?ured in various ways and driven with different circuits, depending on the nature of the signal and the level of performance desired. the TMC1185 has an internal reference that sets the full scale input range of the a/d. the differential input range has each input centered around the common-mode of +2.25v, with each of the two inputs having a full scale range of +1.25v to +3.25v. since each input is 2v peak-to-peak and 180 out of phase with the other, a 4v differential input signal to the quantizer results. as shown in figure 3, the positive full scale reference (reft) and the negative full scale reference (refb) are brought out for external bypass- ing. in addition, the common-mode voltage (cm) may be used as a reference to provide the appropriate offset for the driving circuitry. however, care must be taken not to appreciably load this reference node. for more information regarding external references, single-ended inputs, and input drive circuits, refer to the applications section. figure 3. internal reference structure clock requirements the clk pin accepts a cmos level clock input. both the rising and falling edges of the externally applied clock control the various interstage conversions in the pipeline. therefore, the clock signals jitter, rise/fall times and duty cycle can affect conversion performance. low clock jitter is critical to snr performance in frequency-domain signal environments. clock rise and fall times should be as short as possible (<2ns for best performance). for most applications, the clock duty should be set to 50%. however, for applications requiring no missing codes, a slight skew in the duty cycle will improve dnl performance for conversion rates >35mhz and input frequencies <2mhz (see timing diagram). a possible method for skewing the 50% duty cycle source is shown in figure 4. figure 4. clock skew circuit digital output data the 10-bit output data is provided at cmos logic levels. there is a 6.5 clock cycle data latency from the start convert signal to the valid output data. the standard output coding is straight offset binary where a full scale input signal corresponds to all ?s?at the output. this condition is met with pin 19 ?o?or floating due to an internal pull-down resistor. by applying a high voltage to this pin, a binary twos complement output will be provided where the most signi?ant bit is inverted. the digital outputs of the TMC1185 can be set to a high impedance state by driving oe (pin 18) with a logic ?i? normal operation is achieved with pin 18 ?o?or floating due to an internal pull-down resistor. this function is provided for testability purposes and is not meant to drive digital buses directly or be dynami- cally changed during the conversion process. +1.25v +3.25v 2k w 2k w 0.1 f 0.1 f +2.25v 65-1185-04 reft refb cm TMC1185 to internal comparators 21 22 23 0.1 f r v 2k w v dd 0.1 f v dd clk out clk 65-1185-05 in ic2 ic1 ic1, ic2 = act04 r v = 220 w , typical
TMC1185 product specification 4 table 1. coding table for the TMC1185 note: 1. in the single-ended input mode, +fs = +4.25v and -fs = +0.25v. pin assignments output code differential input (1) sob (pin 19 floating or lo) btc (pin 19 hi) +fs (in = +3.25v, in = +1.25v) 1111111111 0111111111 +fs -1lsb 1111111111 0111111111 +fs -2lsb 1111111110 0111111110 +3/4 full scale 1110000000 0110000000 +1/2 full scale 1100000000 0100000000 +1/4 full scale 1010000000 0010000000 +1lsb 1000000001 0000000001 bipolar zero (in = in = +2.25v) 1000000000 0000000000 -1lsb 0111111111 1111111111 -1/4 full scale 0110000000 1110000000 -1/2 full scale 0100000000 1100000000 -3/4 full scale 0010000000 1010000000 -fs +1 lsb 0000000001 1000000001 -fs (in = +1.25v, in = +3.25v) 0000000000 1000000000 soic ?top view gnd bit 9 (msb) bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) dnc dnc gnd 65-1185-06 gnd in in gnd vdd reft cm refb vdd msbi oe vdd clk vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TMC1185 pin descriptions pin name pin number pin function description b9 2 bit 9, most significant bit b8 3 bit 8 b7 4 bit 7 b6 5 bit 6 b5 6 bit 5 b4 7 bit 4 b3 8 bit 3 b2 9 bit 2 b1 10 bit 1 b0 11 bit 0, least significant bit clk 16 convert clock input, 50% duty cycle cm 22 common-mode voltage. it is derived by (reft + refb)/2. gnd 1, 14, 25, 28 ground in 26 input in 27 complementary input msbi 19 most significant bit inversion, hi: msb inverted for complementary output. lo or floating: straight output. internal pull-down resistor. dnc 12, 13 do not connect.
product specification TMC1185 5 absolute maximum ratings note: 1. stresses above these ratings may permanently damage the device. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. electrostatic discharge can cause damage ranging from performance degrada- tion to complete device failure. fairchild recommends that all integrated circuits be handled, stored and installed using appro - priate esd protection methods. oe 18 hi: high impedance state. lo or floating: normal operation. internal pull-down resistor. refb 21 bottom reference bypass. for external bypassing of internal +1.25v reference. reft 23 top reference bypass. for external bypassing of internal +3.25v reference. vdd 15, 17, 20, 24 +5v power supply parameter min max unit vdd +6 v analog input 0v vdd + 300mv v logic input 0v vdd + 300mv v case temperature +100 c junction temperature +150 c storage temperature +125 c external top reference voltage (reft) +3.4 v external bottom reference voltage (refb) +1.1 v electrical speci?ations at t a = +25 c, vdd = +5v, sampling rate = 40 msps, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. parameter conditions temp min typ max unit resolution 10 bits specified temperature range t ambient ?0 +85 c analog input differential full scale input range +1.25 +3.25 v common-mode voltage 2.25 v analog input bandwidth (?db) small signal -20dbfs (1) input +25 c 120 mhz full power 0db input +25 c 65 mhz input impedance 1.25 || 4 m w || pf digital input logic family ttl/hct compatible cmos falling edge convert command start conversion pin descriptions (continued) pin name pin number pin function description
TMC1185 product specification 6 accuracy (2) gain error +25 c 0.6 1.5 % full 1.1 2.5 % gain tempco 85 ppm/ c power supply rejection of gain delta +vdd = 5% +25 c 0.01 0.15 %fsr/% input offset error full 2.1 3.5 % power supply rejection of offset delta +vdd = 5% +25 c 0.02 0.15 %fsr/% conversion characteristics sample rate 10k 40m sample/s data latency 6.5 convert cyde dynamic characteristics differential linearity error t h = 13ns (3) f = 500khz +25 c 0.5 1.0 lsb 0 c to +70 c 0.6 1.0 lsb f = 12mhz +25 c 0.5 1.0 lsb 0 c to +70 c 0.6 1.0 lsb no missing codes 0 c to +70 c guaran- teed integral linearity error at f = 500khz 0 c to +70 c 0.5 2.0 lsb spurious-free dynamic range (sfdr) f = 500khz (?dbfs input) +25 c 60 70 dbfs full 54 67 dbfs f = 12mhz (?dbfs input) +25 c 58 63 dbfs full 54 62 dbfs two-tone intermodulation distortion (imd) (4) f = 4.4mhz and 4.5mhz (referred to ?dbfs envelope) +25 c full -61 -60 db db signal-to-noise ratio (snr) f = 500khz (?dbfs input) +25 c5759 db full 55 59 db f = 12mhz (?dbfs input) +25 c5658 db full 54 58 db signal-to-(noise + distortion) (sinad) f = 500khz (?dbfs input) +25 c 56 58.5 db full 55 58 db f = 12mhz (?dbfs input) +25 c5357 db full 50 56 db differential gain error ntsc or pal +25 c 0.5 % differential phase error ntsc or pal +25 c 0.1 degrees effective bits (5) f ln = 3.58mhz +25 c 9.3 bits aperture delay time +25 c2 ns aperture jitter +25 c 7 ps rms overvoltage recovery time (6) 1.5x full scale input +25 c2 ns electrical speci?ations (continued) at t a = +25 c, vdd = +5v, sampling rate = 40 msps, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. parameter conditions temp min typ max unit
product specification TMC1185 7 notes: 1. dbfs refers to db below full scale. 2. percentage accuracies are referred to the internal a/d full scale range of 4vp-p. 3. refer to timing diagram footnotes for the f in = 500khz differential linearity error performance condition. 4. imd is referred to the larger of the two input signals. if referred to the peak envelope signal (=0db), the intermodulation products will be 7db better. 5. based on (sinad -1.76)/6.02. 6. no ?ollover?of bits. outputs logic family ttl/hct compatible cmos logic coding logic selectable sob or btc logic levels logic ?o? c l = 15pf full 0 0.4 v logic ?i? c l = 15pf full 2.5 vdd v 3-state enable time 20 40 ns 3-state disable time full 2 10 ns power supply requirements supply voltage: vdd operating full +4.75 +5 +5.25 v supply current: idd operating +25 c7688ma operating full 78 90 ma power consumption operating +25 c 380 460 mw operating full 390 470 mw thermal resistance, q ja 28-pin soic 75 c/w electrical speci?ations (continued) at t a = +25 c, vdd = +5v, sampling rate = 40 msps, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. parameter conditions temp min typ max unit
TMC1185 product specification 8 typical performance curves at t a = +25 c, vdd = +5v, sampling rate = 40 msps, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. spectral performance frequency (mhz) amplitude (db) 0 5 10 15 20 0 ?0 ?0 ?0 ?0 ?00 ?20 f in = 12mhz spectral performance frequency (mhz) amplitude (db) 0 5 10 15 20 0 ?0 ?0 ?0 ?0 ?00 ?20 f in = 500khz spectral performance frequency (mhz) amplitude (db) 0 5 10 15 20 0 ?0 ?0 ?0 ?0 ?00 ?20 f in = 5mhz spectral performance frequency (mhz) amplitude (db) 0 1.0 2.0 3.0 4.0 5.0 0 ?0 ?0 ?0 ?0 ?00 ?20 f in = 1mhz f s = 10msps differential linearity error code dle (lsb) 2.0 1.0 0 ?.0 ?.0 code 0 256 512 768 1024 f in = 500khz differential linearity error code dle (lsb) 2.0 1.0 0 ?.0 ?.0 code 0 256 512 768 1024 65-1185-07 f in = 12mhz
product specification TMC1185 9 typical performance curves (continued) at t a = +25 c, vdd = +5v, sampling rate = 40 msps, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. 0 ?0 ?0 ?0 ?0 ?00 ?20 two-tone intermodulation amplitude (db) 0.0 5.00 10.00 15.00 20.00 frequency (mhz) f 1 = 4.47mhz f 2 = 4.39mhz dynamic performance vs input frequency frequency (mhz) sfdr, snr (db) 70 65 60 55 0.1 1 10 100 sfdr snr 100 80 60 40 20 0 input amplitude (dbm) sfdr (dbfs) swept power sfdr ?0 ?0 ?0 ?0 ?0 0 10 65-1185-08 f in = 12mhz 60 50 40 30 20 10 0 input amplitude (dbm) swept power snr ?0 ?0 ?0 ?0 ?0 0 10 snr (db) f in = 12mhz 4.0 2.0 0 ?.0 ?.0 integral linearity error code ile (lsb) f in = 500khz 0.0 0.20 0.40 0.60 0.80 1.0 65 60 55 50 45 40 dynamic performance vs single-ended full-scale input range dynamic range (db) single-ended full-scale input range (vp-p) snr (f in = 12mhz) sfdr (f in = 500khz) snr (f in = 500khz) sfdr (f in = 12mhz) note: reft ext varied, refb is fixed at the internal value of +1.25v. 234
TMC1185 product specification 10 typical performance curves (continued) at t a = +25 c, vdd = +5v, sampling rate = 40 msps, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. spurious free dynamic range vs temperature ambient temperature ( ? c) sfdr (dbfs) 80 70 60 50 ?0 ?5 0 25 50 75 100 f in = 500khz f in = 12mhz power dissipation vs temperature ambient temperature ( ? c) power (mw) 335 330 325 ?0 ?5 0 25 50 75 100 signal-to-noise ratio vs temperature ambient temperature ( ? c) snr (db) 60 59 58 57 ?0 ?5 0 25 50 75 100 f in = 500khz f in = 12mhz signal-to-(noise + distortion) vs temperature ambient temperature ( ? c) 65-1185-09 sinad (db) 59 58 57 56 ?0 ?5 0 25 50 75 100 f in = 500khz f in = 10mhz supply current vs temperature ambient temperature ( ? c) i q (ma) 67 66 65 ?0 ?5 0 25 50 75 100 75 70 65 60 55 70 dynamic performance vs differential full-scale input range dynamic range (db) 2 3 4 differential full-scale input range (vp-p) note: reft ext varied, refb is fixed at internal value of +1.25v. snr (f in = 500khz) snr (f in = 12mhz) sfdr (f in = 12mhz) sfdr (f in = 500khz)
product specification TMC1185 11 typical performance curves (continued) at t a = +25 c, vdd = +5v, sampling rate = 40 msps, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. gain error vs temperature ambient temperature ( ? c) gain (% fsr) 0 ?.25 ?.5 ?.75 ?.0 ?.25 ?0 ?5 0 25 50 75 100 offset error vs temperature ambient temperature ( ? c) offset (% fsr) ?.75 ?.0 ?.25 ?0 ?5 0 25 50 75 100 track-mode small-signal input bandwidth frequency (hz) track-mode input response (db) 10k 1 0 ? ? ? ? ? 100k 1m 10m 100m 1g output noise histogram (no signal) counts 1.2m 1m 0.8m 0.6m 0.4m 0.2m 0.0 code 65-1185-10 n-2 n-1 n n+1 n+2
TMC1185 product specification 12 timing diagram notes: 1. indicates the portion of the waveform that will stretch out at slower sample rates. 2. t h must be 13ns minimum if no missing codes is desired only for the conditions of t conv 28ns and f in < 2mhz. refer to the clock requirements for a possible clock skew circuit for this condition. symbol description min typ max units t conv convert clock period 25 100 m sns t l clock pulse low 12 12.5 ns t h clock pulse high 12 (2) 12.5 ns t d aperture delay 2 ns t 1 data hold time, c l = 0pf 3.9 ns t 2 new data delay time, c l = 15pf max 12.5 ns track hold "n" hold "n + 1" hold "n + 2" hold "n + 3" hold "n + 4" hold "n + 5 " hold "n + 6" track data valid n-7 data valid n-6 internal track/hold convert clock output data t d t 2 t 1 data latency (6.5 clock cycles) t conv t l t h track track track track n-3 n-5 n-4 n-2 n-1 n track 65-1185-11 track data valid n-8 (1) data invalid applications discussion driving the TMC1185 the TMC1185 has a differential input with a common-mode of +2.25v. for ac-coupled applications, the simplest way to create this differential input is to drive the primary winding of a transformer with a single-ended input. a differential output is created on the secondary if the center tap is tied to the common-mode voltage (cm) of +2.25v per figure 5. this transformer-coupled input arrangement provides good high frequency ac performance. it is important to select a transformer that gives low distortion and does not exhibit core saturation at full scale voltage levels. since the trans- former does not appreciably load the ladder, there is no need to buffer the common-mode (cm) output in this instance. in general, it is advisable to keep the current draw from the cm output pin below 0.5 m a to avoid nonlinearity in the internal reference ladder. a fet input operational ampli?r such as the opa130 can provide a buffered reference for driving external circuitry. the analog in and in inputs should be bypassed with 22pf capacitors to minimize track/hold glitches and to improve high input frequency performance. figure 5. ac-coupled single-ended to differential drive circuit using a transformer figure 6 illustrates another possible low cost interface circuit which utilizes resistors and capacitors in place of a trans- former. depending on the signal bandwidth, the component values should be carefully selected in order to maintain the performance outlined in the data sheet. the input capacitors, c in , and the input resistors, r in , create a high-pass ?ter with the lower corner frequency at f c = 1/(2 p r in c in ). mini-circuits t t1-6-kk81 or equivalent 22 26 27 65-1185-12 cm in in TMC1185 ac input signal 22pf 22pf 0.1pf
product specification TMC1185 13 the corner frequency can be reduced by either increasing the value of r in or c in . if the circuit operates with a 50 w or 75 w impedance level, the resistors are ?ed and only the value of the capacitor can be increased. usually ac-coupling capacitors are electrolytic or tantalum capacitors with values of 1 m f or higher. it should be noted that these large capaci- tors become inductive with increased input frequency, which could lead to signal amplitude errors or oscillation. to main- tain a low ac-coupling impedance throughout the signal band, a small value (e.g. 1 m f) ceramic capacitor could be added in parallel with the polarized capacitor. capacitors c sh1 and c sh2 are used to minimize current glitches resulting from the switching in the input track-and- hold stage and to improve signal-to-noise performance. these capacitors can also be used to establish a low-pass ?ter and effectively reduce the noise bandwidth. in order to create a real pole, resistors r ser1 and r ser2 were added in series with each input. the cut-off frequency of the ?ter is determined by f c = 1/(2 p r ser ?c sh +c adc )) where r ser is the resistor in series with the input, c sh is the external capacitor from the input to ground, and c adc is the internal input capacitance of the a/d converter (typically 4pf). resistors r 1 and r 2 are used to derive the necessary common mode voltage from the buffered top and bottom references. the total load of the resistor string should be selected so that the current does not exceed 1ma. although the circuit in figure 6 uses two resistors of equal value so that the common mode voltage is centered between the top figure 6. ac-coupled differential input circuit figure 7. a low distortion dc-coupled, single-ended to differential input driver circuit TMC1185 *r ser1 49.9 ? r 3 1k ? r 2 (6k ? ) r 1 (6k ? ) c 2 0.1 f c sh1 22pf c sh2 22pf c 3 0.1 f c 1 0.1 f c in 0.1 f v cm c in 0.1 f r in1 25 ? r in2 25 ? *r ser2 49.9 ? +3.25v top reference +1.25v bottom reference in note: * indicates optional component. in 65-1185-13 604 301 w 301 w 301 w 604 w 49.9 w 301 w 604 w 2.49k w 2.49k w +2.25v opa642 opa131 301 w 0.1 f opa642 opa642 +5v ?v +5v 65-1185-14 (2) +5v ?v +5v +5v +5v ?v bas16 (1) bas16 (1) 301 w 24.9 w input level shift buffer optional high impedance input amplifier dc-coupled input signal 26 in 22 cm 27 in TMC1185 notes: (1) a philips bas16 diode or equivalent may be used. (2) supply bypassing not shown. (3) opa620 or opa650 may be substituted. see "driving the TMC1185" section. 22pf 22pf 604 w w 0.1 f 0.1 f (3) (3) (3)
TMC1185 product specification 14 and bottom reference (+2.25v), it is not necessary to do so. in all cases the center point, v cm , should be bypassed to ground in order to provide a low impedance ac ground. if the signal needs to be dc coupled to the input of the TMC1185, an operational ampli?r input circuit is required. in the differential input mode, any single-ended signal must be modi?d to create a differential signal. this can be accomplished by using two operational ampli?rs, one in the noninverting mode for the input and the other ampli?r in the inverting mode for the complementary input. the low distortion circuit in figure 7 will provide the necessary input shifting required for signals centered around ground. it also employs a diode for output level shifting to guarantee a low distortion +3.25v output swing. another dc-coupled circuit is shown in figure 8. other ampli?rs can be used in place of the opa642s if the lowest distortion is not necessary. if out- put level shifting circuits are not used, care must be taken to select operational ampli?rs that give the necessary perfor- mance when swinging to +3.25v with a 5v supply opera- tional ampli?r. the opa620 and opa621, or the lower power opa650 or opa651 can be used in place of the opa642s in figure 7. in that con?uration, the opa650 and opa651 will typically swing to within 100mv of positive full scale. if the opa621 or opa651 is used, the input buffer must be con?ured in a gain of 2. the TMC1185 can also be con?ured with a single-ended input full scale range of +0.25v to +4.25v by tying the complementary input to the common-mode reference voltage as shown in figure 9. this con?uration will result in increased even-order harmonics, especially at higher input frequencies. however, this tradeoff may be quite acceptable for time-domain applications. the driving ampli?r must give adequate performance with a +0.25v to +4.25v output swing in this case. figure 9. single-ended input connection external references and adjustment of fullscale range the internal reference buffers are limited to approximately 1ma of output current. as a result, these internal +1.25v and +3.25v references may be overridden by external references that have at least 25ma of output drive capability. in this instance, the common-mode voltage will be set halfway between the two references. this feature can be used to adjust the gain error, improve gain drift, or to change the full scale input range of the TMC1185. changing the full scale range to a lower value has the bene? of easing the swing requirements of external input ampli?rs. the external references can vary as long as the value of the external top reference (reft ext ) is less than or equal to +3.4v and the value of the external bottom reference (refb ext ) is greater than or equal to +1.1v and the difference between the external references are greater than or equal to 800mv. 22 26 27 cm in in TMC1185 0.1 f single-ended input signal full scale = +0.25v to +4.25v with internal references. 22pf 65-1185-16 figure 8. a wideband dc-coupled, single-ended to differential input driver circuit 50 w 1k w ota opa660 opa660 +1 +1 opa131 1nf ota ?v +5v dc-coupled input signal 27 in 22 cm 26 in TMC1185 note: power supplies and bypassing not shown. the measured snr performance with 12.5mhz input signal is 57db with this driver circuit. 1k w 500 w 500 w 1k w 200 w 243 w 200 w 3b 2 3 6 2 8 5 c 6 6 1 8 5 c e e 3 2 b 200 w c 1 15pf 22pf 65-1185-15 22pf 0.1 f 2k w v out ?v 243 w
product specification TMC1185 15 for the differential con?uration, the full scale input range will be set to the external reference values that are selected. for the single-ended mode, the input range is 2 ?(reft ext ?refb ext ), with the common-mode being centered at (reft ext + refb ext )/2. refer to the typical performance curves for expected performance vs. full scale input range. the circuit in figure 10 works completely on a single +5v supply. as a reference element, it uses the micro-power reference ref1004-2.5, which is set to a quiescent current of 0.1ma. ampli?r a 2 is con?ured as a follower to buffer the +1.25v generated from the resistor divider. to provide the necessary current drive, a pull-down resistor, r p is added. ampli?r a 1 is con?ured as an adjustable gain stage, with a range of approximately 1 to 1.32. the pull-up resistor again relieves the op amp from providing the full current drive. the value of the pull-up/down resistors is not critical and can be varied to optimize power consumption. the need for pull-up/down resistors depends only on the drive capability of the selected drive ampli?r and thus can be omitted. pc board layout and bypassing a well-designed, clean pc board layout will assure proper operation and clean spectral response. proper grounding and bypassing, short lead lengths, and the use of ground planes are particularly important for high frequency circuits. multilayer pc boards are recommended for best perfor- mance but if carefully designed, a two-sided pc board with large, heavy ground planes can give excellent results. it is recommended that the analog and digital ground pins of the TMC1185 be connected directly to the analog ground plane. in our experience, this gives the most consistent results. the a/d power supply commons should be tied together at the analog ground plane. power supplies should be bypassed with 0.1 m f ceramic capacitors as close to the pin as possible. dynamic performance testing the TMC1185 is a high performance converter and careful attention to test techniques is necessary to achieve accurate results. highly accurate phase-locked signal sources allow high resolution fft measurements to be made without using data windowing functions. a low jitter signal generator such as the hp8644a for the test signal, phase-locked with a low jitter hp8022a pulse generator for the a/d clock, gives excellent results. low pass ?tering (or bandpass ?tering) of test signals is absolutely necessary to test the low distortion of the TMC1185. using a signal amplitude slightly lower than full scale will allow a small amount of ?eadroom?so that noise or dc offset voltage will not overrange the a/d and cause clipping on signal peaks. figure 10. optional external reference to set the full-scale range utilizing a dual, single-supply op amp 2k w +2.5v to +3.25v +5v +5v r p 220 w r p 220 w 10k w 6.2k w 0.1 m f +2.5v 10k w 1/2 opa2234 1/2 opa2234 a 1 a 2 bottom reference 65-1185-17 top reference ref1004 +1.25v 10k w 10k w * 10k w * note: (*) use parts alternatively for adjustment capability.
TMC1185 product specification 16 dynamic performance de?itions 1. signal-to-noise-and-distortion ratio (sinad): 2. signal-to-noise ratio (snr): 3. intermodulation distortion (imd): imd is referenced to the larger of the test signals f 1 or f 2 . five ?ins?either side of peak are used for calculation of fundamental and harmonic power. the ??frequency bin (dc) is not included in these calculations as it is of little importance in dynamic signal processing applications. 10 sinewave signal power noise harmonic power (first 15 harmonics) + -------------------------------------------------------------------------------------------------------------- log 10 sinewave signal power noisepower -------------------------------------------------------- - log 10 highest imd product power (to 5th-order) sinewave signal power ------------------------------------------------------------------------------------------------------ log figure 11. TMC1185 interface schematic with ac-coupling and external buffers gnd dnc dnc lsb msb gnd 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 1 19 vdd vdd vdd vdd clk oe msbi refb cm reft gnd in in gnd 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TMC1185 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f r 1 50 w r 2 50 w ext clk 65-1185-18 ac input signal 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 dir g+ 1 19 dir g+ 74fct2245 74fct2245 mini-circuits tt1-6-kk81 or equivalent 22pf 22pf (1) note: (1) all capacitors should be located as close to the pins as the manufacturing process will allow. ceramic x7r surface-mount capacitors or equivalent are recommended. +5v dynamic performance de?itions 1. signal-to-noise-and-distortion ratio (sinad): 2. signal-to-noise ratio (snr): 3. intermodulation distortion (imd): imd is referenced to the larger of the test signals f 1 or f 2 . five ?ins?either side of peak are used for calculation of fundamental and harmonic power. the ??frequency bin (dc) is not included in these calculations as it is of little importance in dynamic signal processing applications. 10 sinewave signal power noise harmonic power (first 15 harmonics) + -------------------------------------------------------------------------------------------------------------- log 10 sinewave signal power noisepower -------------------------------------------------------- - log 10 highest imd product power (to 5th-order) sinewave signal power ------------------------------------------------------------------------------------------------------ log
product specification TMC1185 17 output to genlock 65-1185-19 y/comp input s-vhs chroma input y/composite lpf and clamp circuit chrominance bpf and clamp circuit sw1 10 bit adc TMC1185 10 bit adc TMC1185 sw2 tmc2242 96 way edge connector 1 32 tmc2242 video capture the TMC1185 should be used for digitizing video data in high quality, professional video designs prior to feeding data into fairchilds digital mixers (tmc2080, tmc2081) or tmc22x5y decoder family. fairchild offers an analog video front end design, both schematics and artwork, to assist designers in designing a high performance video system. for more information contact your fairchild sales represen- tative or e-mail applications@lj.sd.ray.com. figure 12. 10-bit video capture reference design
TMC1185 product specification 18 notes:
product specification TMC1185 19 mechanical dimensions 28 lead soic package 28 13 112 a .0926 .1043 2.35 2.65 symbol inches min. max. min. max. millimeters notes a1 .004 .0118 0.10 0.30 .020 0.51 b .013 0.33 c .0091 .0125 0.23 0.32 e .2914 .2992 7.40 7.60 e .398 .419 10.11 10.65 .010 .0295 0.25 0.75 h .050 bsc 1.27 bsc h l .020 .040 0.508 1.02 0 ? 8 ? 0 ? 8 ? 5 4 6 7 2 3 n28 28 a d .6969 .7125 17.70 18.10 notes: 1. 2. 3. 4. 5. 6. 7. 8. dimensioning and tolerancing per ansi y14.5m-1982. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed .006 in. (0.15mm) per side. dimension e does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed .010 in. (0.25mm) per side. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. l is the length of terminal for soldering to a substrate. n is the number of terminal positions. the lead width b, as measured .014 in. (0.36 mm) or greater above the seating plane, shall not exceed a maximum value of 0.24 in. (0.61 mm). lead to lead coplanarity shall be less than .004 in. (0.10 mm) from seating plane. h e a d e b a1 ?c .004 (.10) .010 (.25) a c seating plane base plane a h x 45 ? see detail ? detail ? l c m m b s
TMC1185 product specification 5/20/98 0.0m 001 stock# ds70001185 1998 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1 . life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2 . a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com o r dering in f ormation p r oduct number p a c k age TMC1185ndc40 28 pin soic

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